Parallel-load 8-bit Shift Registers

  /ordering information The ?LV165A devices are parallel-load, 8-bit Shift Registers designed for 2-V to 5.5-V VCC operation. When the devices are clocked, data is shifted toward the serial output QH. Parallel-in access to each stage is provided by eight individual direct data inputs that are enabled by a low level at the shift/load (SH/ LD) input. The ?LV165A devices feature a clock-inhibit function and a complemented serial output, QH. ORDERING INFORMATION TA PACKAGE? QFN ? RGY SOIC ? D SOP ? NS ?40?C to 85 C ?40 C 85?C SSOP ? DB Reel of 1000 Tube of 40 Reel of 2500 Reel of 2000 Reel of 2000 Tube of 90 TSSOP ? PW TVSOP ? DGV CDIP ? J ?55 C 125?C ?55?C to 125 C CFP ? W Reel of 2000 Reel of 250 Reel of 2000 Tube of 25 Tube of 150 LCCC ? FK Tube of 55 SNJ54LV165AFK SNJ54LV165AFK ? Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 ? DALLAS, TEXAS 75265 GND NC QH SER 1 SN54LV165A SN74LV165A PARALLEL LOAD 8 BIT Shift Registers SCLS402K ? APRIL 1998 ? REVISED APRIL 2005
Item: SN54LV165A
File Size : 93 KB
Pages : 19 Pages

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