Dual J-negative-edge-triggered Flip-flops With Clear And Preset

  /ordering information The ?HC112 devices contain two independent J-K negative-edge-triggered Flip-Flops A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the J and K inputs meeting the setup time requirements are transferred to the outputs on the negative-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the fall time of the CLK pulse. Following the hold-time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. These versatile Flip-Flops perform as toggle Flip-Flops by tying J and K high.
Item: SNJ54HC112
File Size : 55 KB
Pages : 13 Pages

Other Part Numbers in this pdf file

SNJ54HC112W   SNJ54HC112J   SNJ54HC112FK   SN54HC112J  
Texas Instruments Incorporated
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