quad receive chip contains four identical down-conversion Circuits
Each down-convert circuit accepts a real sample rate up to 62.5 MHz, down converts a selected carrier frequency to zero, decimates the signal rate by a programmable factor ranging from 16 to 32768 (32 to 65,536 for complex outputs), and optionally sums it with other down converted samples. The chip outputs the four down-converted signals, or their sum. The chip contains a user programmable output Filter
which can be used to arbitrarily shape the received data?s spectrum. This Filter
can be used as a Nyquist receive Filter
for digital data transmission. Two down-converter paths can be merged to be used as a single complex input down-conversion circuit. The down-converters are designed to maintain over 95 dB of spur free dynamic range and over 100 dB of out of band rejection. Each down-convert circuit accepts 16 bit inputs and produces 16 bit outputs (bit serial). The frequencies and phase offsets of the four sine/cosine sequence generators can be independently specified, as can the gain of each circuit. The down converters share the same bandwidth, Filter
coefficients and input formats. A special mode allows the Downconverters
to support GSM and DAMPS blocker requirements (see Sections 7.5 and 7.6).