Fabricated in 0.5 micron CMOS technology, the GC3021A
chip is designed to mix input data with an internally generated sine/cosine sequence. The chip can be used as a signal mixer, or if the phase error lookup and phase lock loop (PLL) circuitry is enabled, as a carrier removal circuit for signal demodulation. The mixer accepts complex data at rates up to 100 MHz , or real samples at rates up to 200 MHz in the real input mode . The chip mixes the input with a complex sinusoid, and outputs the results at a 100 MHz rate. The input data in the real mode is assumed to be even/odd sample pairs. The 200 MHz input data is split into even and odd samples streams, each at a rate of 100 million samples per second. The even and odd time sample data streams are mixed with sines and cosines which have also been split into even and odd time streams. The complex results are then output as two complex pairs at 100 MHz, one for the even time samples and one for the odd time samples. The frequency of the sine/cosine sequence is specified as a 32 bit phase word which drives a phase accumulator. A carry input to the phase accumulator allows the user to extend the tuning resolution with an external accumulator. The GC3021A
chip?s carrier removal mode allows the chip to be used as part of a QPSK/QAM Demodulator
using decision error feed back to achieve carrier lock. A phase error feedback circuit uses the upper 7 bits of the I and Q mixer outputs to lookup a one bit phase error term. The phase error lookup is performed by mapping the I/Q pair into a single quadrant so that the lookup table address is only 12 bits (6 bits of I and 6 bits of Q). The 4096 bit lookup table is programmed by the user to output the sign of the phase error for each possible I/Q pair. This phase error feeds a phase-lock-loop (PLL) circuit which adjusts the sinusoid frequency to drive the average phase error to zero.