The Harris CD74HC259
Addressable Latch features the low-power consumption associated with CMOS circuitry and has speeds comparable to low-power Schottky. This Latches
three active modes and one reset mode. When both the Latch Enable (LE) and Master Reset (MR) inputs are low (8-line Demultiplexer mode) the output of the addressed latch follows the Data input and all other outputs are forced low. When both MR and LE are high (Memory Mode), all outputs are isolated from the Data input, i.e., all Latches
hold the last data presented before the LE transition from low to high. A condition of LE low and MR high (Addressable Latch mode) allows the addressed latch?s output to follow the data input; all other Latches
are unaffected. The Reset mode (all outputs low) results when LE is high and MR is low.