Dual J-k Flip-flop With Reset Negative-edge Trigger

  The ?HC107 and CD74HCT107 utilize silicon Gate CMOS technology to achieve operating speeds equivalent to LSTTL parts. They exhibit the low power consumption of standard CMOS integrated Circuits together with the ability to drive 10 LSTTL loads. These ?ip-?ops have independent J, K, Reset and Clock inputs and Q and Q outputs. They change state on the negative-going transition of the clock pulse. Reset is accomplished asynchronously by a low level input. This device is functionally identical to the HC/HCT73 but differs in terminal assignment and in some parametric limits. The HCT logic family is functionally as well as pin compatible with the standard LS family.
Item: CD54HC107
File Size : 60 KB
Pages : 15 Pages

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Texas Instruments Incorporated
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