4-bit Synchronous Binary Counters

  The clear function is asynchronous. A low level at the clear (CLR) input sets all four of the Flip-Flop outputs low, regardless of the levels of the CLK, load (LOAD), or enable inputs. The carry look-ahead circuitry provides for cascading Counters for n-bit synchronous applications without additional gating. Instrumental in accomplishing this function are ENP, ENT, and a ripple-carry output (RCO). Both ENP and ENT must be high to count, and ENT is fed forward to enable RCO. Enabling RCO produces a high-level pulse while the count is maximum (9 or 15, with QA high). This high-level overflow ripple-carry pulse can be used to enable successive cascaded stages. Transitions at ENP or ENT are allowed, regardless of the level of CLK. The Counters feature a fully independent clock circuit. Changes at control inputs (ENP, ENT, or LOAD) that modify the operating mode have no effect on the contents of the Counter until clocking occurs. The function of the Counter (whether enabled, disabled, loading, or counting) is dictated solely by the conditions meeting the stable setup and hold times.
Item: CD54AC161
File Size : 51 KB
Pages : 15 Pages

Other Part Numbers in this pdf file

CD54AC161F3A   AC161M  
Texas Instruments Incorporated
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