Fixed-point Digital Signal Processors

  The TMS320C64x? DSPs (including the TMS320C6414 TMS320C6415 and TMS320C6416 devices) are the highest-performance fixed-point DSP generation in the TMS320C6000 DSP platform. The TMS320C64x? (C64x??) device is based on the second-generation high-performance, advanced VelociTI? very-long-instruction-word (VLIW) architecture (VelociTI.2?) developed by Texas Instruments (TI), making these DSPs an excellent choice for multichannel and multifunction applications. The C64x? is a code-compatible member of the C6000? DSP platform. With performance of up to 5760 million instructions per second (MIPS) at a clock rate of 720 MHz, the C64x devices offer cost-effective solutions to high-performance DSP programming challenges. The C64x DSPs possess the operational flexibility of high-speed controllers and the numerical capability of array processors. The C64x? DSP core processor has 64 general-purpose Registers of 32-bit word length and eight highly independent functional units?two multipliers for a 32-bit result and six arithmetic logic units (ALUs)? with VelociTI.2? extensions. The VelociTI.2? extensions in the eight functional units include new instructions to accelerate the performance in key applications and extend the parallelism of the VelociTI? architecture. The C64x can produce four 16-bit multiply-accumulates (MACs) per cycle for a total of 2880 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 5760 MMACS. The C64x DSP also has application-specific hardware logic, on-chip Memory and additional on-chip peripherals similar to the other C6000? DSP platform devices. The C6416 device has two high-performance embedded coprocessors [Viterbi Decoder Coprocessor (VCP) and Turbo Decoder Coprocessor (TCP)] that significantly speed up channel-decoding operations on-chip. The VCP operating at CPU clock divided-by-4 can decode over 600 7.95-Kbps adaptive multi-rate (AMR) [K = 9, R = 1/3] voice channels. The VCP supports constraint lengths K = 5, 6, 7, 8, and 9, rates R = 1/2, 1/3, and 1/4, and flexible polynomials, while generating hard decisions or soft decisions. The TCP operating at CPU clock divided-by-2 can decode up to forty-three 384-Kbps or seven 2-Mbps turbo encoded channels (assuming 6 iterations). The TCP implements the max*log-map algorithm and is designed to support all polynomials and rates required by Third-Generation Partnership Projects (3GPP and 3GPP2), with fully programmable frame length and turbo interleaver. Decoding parameters such as the number of iterations and stopping criteria are also programmable. Communications between the VCP/TCP and the CPU are carried out through the EDMA controller.
Item: TMP320C6414
File Size : 274 KB
Pages : 139 Pages

Other Part Numbers in this pdf file

Texas Instruments Incorporated
Draw TMP320C6414 Schematic Online for Free