The THC63LVD104C Receiver
is designed to support pixel data transmission between Host and Flat Panel Display from NTSC up to SXGA resolutions. The THC63LVD104C
converts the LVDS
data streams back into 35bits of CMOS/TTL data with the choice of the rising edge or falling edge clock for the convenience with a variety of LCD panel controllers.At a transmit clock frequency of 112MHz, 30bits of RGB data and 5bits of timing and control data (HSYNC, VSYNC,DE,CNTL1,CNTL2) are transmitted at an effective rate of 784Mbps per LVDS
channel.Using a 112MHz clock, the data throughput is 490Mbytes per second.