The V58C2512(804/404/164)SD is a four bank DDR DRAM
organized as 4 banks x 16Mbit x 8 (804), 4 banks x 32Mbit x 4 (404), 4 banks x 8Mbit x 16 (164). The V58C2512(804/404/164)SD achieves high speed data transfer rates by employing a chip architecture that prefetches multiple bits and then synchronizes the output data to a system clock. All of the control, address, Circuits
are synchronized with the positive edge of an externally supplied clock. I/O transactions are occurring on both edges of DQS. Operating the four Memory
banks in an interleaved fashion allows random access operation to occur at a higher rate than is possible with standard DRAMs
A se- quential and gapless data rate is possible depending on burst length, CAS latency and speed grade of the device.