This 20-bit universal Bus Driver
is designed for 1.65-V to 3.6-V VCC operation. Data flow from A to Y is controlled by the output-enable (OE) input. The device operates in the transparent mode when the latch-enable (LE) input is low. The A data is latched if the clock (CLK) input is held at a high or low logic level. If LE is high, the A data is stored in the latch Flip-Flop
on the low-to-high transition of CLK. When OE is high, the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the Resistor
is determined by the current-sinking capability of the driver. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. The SN74ALVCH16836
is characterized for operation from ?40?C to 85?C.