9-bit Bus-interface Flip-flops With 3-state Outputs

  designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing wider Buffer Registers I/O ports, bidirectional Bus Drivers parity bus interfacing, and working Registers With the clock-enable (CLKEN) input low, the nine D-type edge-triggered Flip-Flops enter data on the low-to-high transitions of the clock (CLK) input. Taking CLKEN high disables the clock Buffer latching the outputs. The ?ALS29823 have noninverting data (D) inputs. Taking the clear (CLR) input low causes the nine Q outputs to go low independently of the clock. A buffered output-enable (OE) input places the nine outputs in either a normal logic state (high or low logic levels) or a high-impedance state. The outputs also are in the high-impedance state during power-up and power-down conditions. The outputs remain in the high-impedance state while the device is powered down. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without Interface or pullup components. OE does not affect the internal operation of the Flip-Flops Old data can be retained or new data can be entered while the outputs are in the high-impedance state. The SN54ALS29823 is characterized for operation over the full military temperature range of ?55?C to 125?C. The SN74ALS29823 is characterized for operation from 0?C to 70?C.
Item: SN74ALS29823
File Size : 13 KB
Pages : 7 Pages

Other Part Numbers in this pdf file

Texas Instruments Incorporated
Draw SN74ALS29823 Schematic Online for Free