feature a fully independent clock circuit. Changes at the control inputs (CTEN and D/U) that will modify the operating mode have no effect on the contents of the Counter
until clocking occurs. The function of the Counter
will be dictated solely by the condition meeting the stable setup and hold times. These Counters
are fully programmable; that is, the outputs may each be preset to either level by placing a low on the load input and entering the desired data at the data inputs. The output will change to agree with the data inputs independently of the level of the clock input. This feature allows the Counters
to be used as modulo-N dividers by simply modifying the count length with the preset inputs. The CLK, D/U, and LOAD inputs are buffered to lower the drive requirement, which significantly reduces the loading on, or current required by, Clock Drivers
etc., for long parallel words. Two outputs have been made available to perform the cascading function: ripple clock and maximum/minimum count. The latter output produces a high-level output pulse with a duration approximately equal to one complete cycle of the clock while the count is zero (all outputs low) counting down or maximum (9 or 15) counting up. The ripple clock output produces a low-level output pulse under those same conditions but only while the clock input is low. The Counters
can be easily cascaded by feeding the ripple clock output to the enable input of the succeeding Counter
if parallel clocking is used, or to the clock input if parallel enabling is used. The maximum/minimum count output can be used to accomplish look-ahead for high-speed operation.