256 ? 9, 512 ? 9, 1024 ? 9 Asynchronous First-in, First-out Memories

  The SN74ACT7200L SN74ACT7201LA and SN74ACT7202LA are constructed with dual-port SRAM and have internal write and read address Counters to provide data throughput on a first-in, first-out (FIFO) basis. Write and read operations are independent and can be asynchronous or coincident. Empty and full status flags prevent underflow and overflow of Memory and depth-expansion logic allows combining the storage cells of two or more devices into one FIFO Word-width expansion is also possible. Data is loaded into Memory by the write-enable (W) input and unloaded by the read-enable (R) input. Read and write cycle times of 25 ns (40 MHz) are possible with data access times of 15 ns.
Texas Instruments Incorporated
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