ten bit, D-Type, three-state, positive edge triggered ?ip-?ops use a small geometry BiCMOS technology. The output stage is a combination of bipolar and CMOS Transistors
that limits the output HIGH level to two Diode
drops below VCC. This resultant lowering of output swing (0V to 3.7V) reduces power bus ringing (a source of EMI) and minimizes VCC bounce and ground bounce and their effects during simultaneous output switching. The output con?guration also enhances switching speed and is capable of sinking 48 milliamperes. The ten ?ip-?ops enter data into their Registers
on the LOW to HIGH transition of the clock(CP). The Output Enable (OE) controls the three state outputs and is independent of the Register
operation. When the Output Enable (OE) is HIGH, the outputs are in the high impedance state. The CD74FCT821A
share the same con?gurations, but the CD74FCT821A
outputs are noninverted while the CD74FCT822A
devices have inverted outputs.