is a high-performance Clock Synthesizer
driver that generates all required clock signals necessary for a high-performance PC motherboard. The four central processing unit (CPU) clock outputs (PCLKn) are programmable to one of three frequencies (50 MHz, 60 MHz, or 66 MHz) via the SEL0 and SEL1 control inputs. The six peripheral-component-interconnect (PCI) clock outputs (BCLKn) are half the frequency of PCLKn and are delayed 1 ns to 4 ns from the rising edge of the CPU clock. In addition, the four fixed-frequency outputs provide a 24-MHz clock (CLK24), a 12-MHz clock (CLK12), and two buffered copies of the 14.318-MHz input reference (REF0, REF1). The CDC9841
generates all output frequencies from a 14.31818-MHz crystal input. A reference clock can be provided at X1 instead of a crystal input. Two phase-lock loops (PLLs) generate the CPU clock frequency and the 24-MHz clock frequency. On-chip loop Filters
and internal feedback eliminate the need for external components. The PCI
and 12-MHz clock frequencies are derived from the base CPU and 24-MHz clock frequencies, respectively. The PLL circuit can be bypassed in the TEST mode (i.e., SEL0 = SEL1 = H) to distribute a test clock provided at the X1 input. Because the CDC9841
is based on PLL circuitry, it requires a stabilization time to achieve phase lock of the PLL. This stabilization time is required following power up and application of a fixed-frequency, fixed-phase signal at the X1 input, as well as following any changes to the SELn inputs. PCLKn and BCLKn provide low-skew/low-jitter clock signals for reliable clock operation. All outputs are 3 state and are enabled via OE.