This section describes the main features of the TMS320VC5507
lists the pin assignments, and describes the function of each pin. This data manual also provides a detailed description section, electrical specifications, parameter measurement information, and mechanical data about the available packaging. NOTE: This data manual is designed to be used in conjunction with theTMS320C55x? DSP
Functional Overview (literature number SPRU312), the TMS320C55x DSP
CPU Reference Guide (literature number SPRU371), and the TMS320C55x DSP
Peripherals Overview Reference Guide (literature number SPRU317). 2.1 Description The TMS320VC5507
fixed-point digital signal processor (DSP) is based on the TMS320C55x DSP
generation CPU processor core. The C55x? DSP
architecture achieves high performance and low power through increased parallelism and total focus on reduction in power dissipation. The CPU supports an internal bus structure that is composed of one program bus, three data read buses, two data write buses, and additional buses dedicated to peripheral and DMA activity. These buses provide the ability to perform up to three data reads and two data writes in a single cycle. In parallel, the DMA controller can perform up to two data transfers per cycle independent of the CPU activity. The C55x CPU provides two multiply-accumulate (MAC) units, each capable of 17-bit x 17-bit multiplication in a single cycle. A central 40-bit arithmetic/logic unit (ALU) is supported by an additional 16-bit ALU. Use of the ALUs is under instruction set control, providing the ability to optimize parallel activity and power consumption. These resources are managed in the Address Unit (AU) and Data Unit (DU) of the C55x CPU.