device, which provide the most cost-effective solution for the solid state mass storage market, is offered with core power supply (VDD) and input/output power supply (VDDQ) of 3.3V. The device operates from a 3V power supply. The address lines are multiplexed with the data input/output signals on a multiplexed x8 input/output bus. This Interface
reduces the pin count and makes it possible to migrate to other densities without changing the footprint. The Memory
is divided into blocks that can be erased independently. It is possible, therefore, to preserve valid data while old data are erased. The 16-Gbit device includes 4096 blocks. Each block is composed by 128 pages consisting of two NAND structures of 32 series connected Flash
cells. Every cell holds two bits. The Memory
array is split into 2 planes. This multiplane architecture makes it possible to program 2 pages at a time (one in each plane), to erase 2 blocks at a time (one in each plane), or to read 2 pages at a time (one in each plane) dividing by two the average program, erase, and read times. The device has the Chip Enable ?don?t care? feature, which allows the bus to be shared between more than one Memory
at the same time, as Chip Enable transition during the latency time do not stop the read operation. Program and erase operations can never be interrupted by Chip Enable transition.