is a low cost, low jitter, high performance Clock Synthesizer
for networking applications. Using analog Phase-Locked Loop (PLL) techniques, the device accepts a 12.5 MHz or 25 MHz clock or fundamental mode crystal input to produce multiple output clocks for networking chips, PCI
outputs all have zero ppm synthesis error. The ICS650-27
is pin compatible and functionally equivalent to the ICS650-07. It is a performance upgrade and is recommended for all new 3.3V designs. See the MK74CB214 ICS551
for non-PLL Buffer
devices which produce multiple low-skew copies of these output clocks. See the ICS570 ICS9112-16
17/18 for zero delay Buffers
that can synchronize outputs and other needed clocks.