Networking Clock Source

  The ICS650-27 is a low cost, low jitter, high performance Clock Synthesizer for networking applications. Using analog Phase-Locked Loop (PLL) techniques, the device accepts a 12.5 MHz or 25 MHz clock or fundamental mode crystal input to produce multiple output clocks for networking chips, PCI devices, SDRAM and ASICs The ICS650-27 outputs all have zero ppm synthesis error. The ICS650-27 is pin compatible and functionally equivalent to the ICS650-07. It is a performance upgrade and is recommended for all new 3.3V designs. See the MK74CB214 ICS551 and ICS552-01 for non-PLL Buffer devices which produce multiple low-skew copies of these output clocks. See the ICS570 ICS9112-16 17/18 for zero delay Buffers that can synchronize outputs and other needed clocks.
Item: ICS650-27
File Size : 25 KB
Pages : 7 Pages

Other Part Numbers in this pdf file

650R-27IT   650R-27ILFT   650R-27ILF   650R-27I  
Integrated Device Technology
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